The present invention relates generally to the formation of integrated circuit structures, and particularly, but not by way of limitation, to methods for forming dual damascene structures.
With the advent of ultra large-scale integration (ULSI) circuits, the number of interconnections in a semiconductor substrate has increased astronomically. The interconnections are made between passive and active devices within the substrate, as well as between a multitude of wiring layers that constitute the circuits on the substrate. The dual damascene process is a well-known technique for forming interconnections in semiconductor devices. The dual damascene process creates both the vias and lines for each metal layer by etching vias and trenches in the dielectric layer, depositing a conductor such as copper in the etched features and using a planarization process such as chemical mechanical planarization (CMP) to remove the excess copper.
There are many possible scenarios for a dual damascene process flow. FIGS. 1a–1g illustrate a prior art method for forming a damascene structure. In FIG. 1a, a via hole pattern having an opening 5 has been formed in first photoresist layer 40 on a stack consisting of anti-reflective coating layer 30, dielectric layer 20, etch stop layer 10, and a substrate (not shown). The via hole pattern is etch transferred through the underlying layers consisting of anti-reflective coating layer 30 and dielectric layer 20 and partially transferred through etch stop layer 10 to form a via hole as shown in FIG. 1b. After first photoresist layer 40 is stripped, a sacrificial via fill layer 50 is filled in the via hole with overburden and thereafter, a second photoresist layer 60 having a trench pattern with opening 6 is formed above the sacrificial via fill layer 50 as depicted in FIGS. 1c and 1d. The trench pattern is etch transferred through sacrificial via fill layer 50, anti-reflective coating layer 30 and partially through dielectric layer 20 to form a trench. It is understood that one function of the sacrificial via fill layer is to decrease the etching rate of dielectric layer 20. Second photoresist layer 60 and sacrificial via fill layer 50 may thereafter be removed by dry plasma ash or wet chemistry and the remaining structure is shown in FIG. 1e. FIG. 1f shows that the remaining etch stop layer 10 completely removed by dry plasma ash or wet chemistry. A conductive layer 70 is thereafter deposited to fill via and trench openings and after a planarization step, the completed damascene structure appears as illustrated in FIG. 1g. 
While dual damascene methods are desirable in semiconductor device fabrication, dual damascene methods are nonetheless not entirely without problems. One such problem that may occur is during the process of removing the photoresist, the etch stop layer, or the sacrificial via fill layer. Conventionally, photoresist may be removed by either dry plasma ash or wet chemistry. If dry plasma ash is utilized however, such as by ashing in an oxygen (O2) plasma, a number of defects may occur on the wafer or trench surface. One such defect is damage to the dielectric layer in that the dielectric constant k (commonly less than 4) of the dielectric layer typically increases which then increases the overall dielectric constant of the dual damascene structure. This has the adverse effect of increasing the RC delay which in turn degrade circuit performance. Another defect that may occur in damascene patterning is the development of trench surface micro-roughening as shown in FIG. 1f when the etch stop layer is removed by dry plasma ash. Yet another defect is the occurrence of micro-trenching on the trench surface. Both the micro-roughening and the micro-trenching are small-scale deviation of the trench surface from a nominal plane surface, with many small, closely spaced peaks and valleys. They are undesirable and create IC performance and delay problems by causing additional processing and costly rework before a clean via hole and/or trench opening can be achieved and metal deposition can proceed.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved method of forming dual damascene structures that have an overall low dielectric constant, reduced RC delay characteristics and avoids the reliability and IC performance problems associated with conventional methods of forming dual damascene structures.